Automaticaly Organize Your Photos by Date

Now that summer is over and your digital camera is full of pictures, how do you get them organized? At the command line of course! The script provided here automatically organizes them into sub-directories by date.

After my digital camera fills up with pictures, usually after a few weeks or months, I download them to my Ubuntu system. Usually they all end up in one directory. I find it more helpful to sort the image files by the date they were taken: most of the time I want to geotag them and usually photos that were taken on the same day are likely to have been taken in the same location also.

The following short script goes through the .jpg files in the current directory and gets the date stored within each image. It then creates a directory corresponding to the date (in case it doesn’t exist) in the format year/month/day (all numeric) and copies the image into that directory. So for example, a photo called IMG_001.jpg taken on July 4th 2009 will end up under the path 2009/07/04/IMG_001.jpg.

The script requires the IMageMagick package, but that shouldn’t be a problem on recent distributions.

# Goes through all jpeg files in current directory, grabs date from each
# and sorts them into subdirectories according to the date
# Creates subdirectories corresponding to the dates as necessary.
for fil in *.jpg
# Also try *.JPG
datepath="$(identify -verbose $fil | grep DateTimeOri | awk '{print $2 }' | sed s%:%/%g)"
if ! test -e "$datepath"; then
mkdir -pv "$datepath"   fi
mv -v $fil $datepathdone

Send an Email Alert When Your Disk Space Gets Low

If you don’t want to step up to a full monitoring solution such as Nagios you can create your own scripts for monitoring the things that you want to monitor, such as disk space. The following script alerts you when your root partition is almost full:

#!/bin/bashCURRENT=$(df / | grep / | awk '{ print $5}' | sed 's/%//g')
if [ "$CURRENT" -gt "$THRESHOLD" ] ;
then   mail -s 'Disk Space Alert' <<
EOF "Your root partition remaining free
space is critically low. Used: $CURRENT" EOF

The script sends an email when the disk usage rises above the percentage specified by the THRESHOLD varialbe (90% here).

To run it daily, for example, save the script to the file in your home directory, change the email to your email, and add the following line at the end of /etc/crontab file:

@daily ~/

ARM Cortex-A9 MPCore is out

The ARM Cortex-A9 MPCore Cortex-A9MP_diag_small

multicore processor integrates the proven and highly successful ARM MPCore technology along with further enhancements to simplify and broaden the adoption of multicore solutions. The Cortex-A9 MPCore provides the ability to extend peak performance to unprecedented levels while also supporting design flexibility and new features to further reduce and control the power consumption at the processor and system level. Targeted implementations of the Cortex-A9 MPCore can also offer mobile devices increased peak performance over today’s solutions by utilizing the design flexibility and advanced power management techniques offered by the ARM MPCore technology to maintain operation within the tight mobile power budgets.
View larger block diagram

Using the scalable peak performance, this processor is able to exceed the performance of today’s comparable high-performance embedded devices and brings a consistent software investment over an extended breadth of markets.

Both the Cortex-A9MPCore and the Cortex-A9 application-class processors are supported by a rich set of features and ARMv7 architectural functionality so as to deliver a high-performance and low-power solution across both application specific and general purpose designs.

In addition, the Cortex-A9 MPCore processor is available as a speed or power optimized hard macro implementation delivering multi GHz performance with industry-leading low power consumption.



High-Efficiency Superscalar Pipeline

Industry leading performance with over 2.0 DMIPS/MHz for unprecedented peak performance while also maintaining low power for extended battery life and lower cost packaging and operation

NEON Media Processing Engine

Accelerating media and signal processing functions for increased application specific performance with the convenience of consolidated application software development and support

Floating-Point Unit

Provides significant acceleration for both single and double precision scalar Floating-Point operations. Double the performance of previous ARM FPU, this unit provides industry leading image processing, graphics and scientific computation capabilities

Optimized Level 1 Caches

Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. Also providing the option for cache coherence for enhanced inter-processor communication or support of rich SMP capable OS for simplified multicore software development

Thumb®-2 Technology

Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions

TrustZone® Technology

Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry Partners

Jazelle® RCT and DBX Technology

Provides up to 3x reduction on code size for Just-in-time (JIT) and ahead-of-time compilation of bytecode languages while also supporting direct byte code execution of Java instructions for acceleration in traditional virtual machines

L2 Cache Controller

Providing low latency and high bandwidth access to up to 2 MB of cached memory in high frequency designs, or design needing to reduce the power consumption associated with off chip memory access

Program Trace Macrocell and CoreSight™ Design Kit

Together these components provide the software developer with the ability to non-obtrusively trace the execution history of multiple processors and either store this, along with time stamped correlation, into an on-chip buffer, or off chip through a standard trace interface so as to have improved visibility during development and debug

The Cortex-A9 MPCore processor is the first ARM processor to combine the Cortex application class architecture with multiprocessing capabilities for scalable performance and provides enhanced multicore technology that includes:

  • Accelerator Coherence Port (ACP) for increased system performance and lower system power
  • Advanced Bus Interface Unit for low latency in high bandwidth devices
  • Multicore TrustZone® technology with interrupt virtualization to enable hardware based security and enhanced paravirtualization solutions
  • Generalized Interrupt Controller (GIC) for software portability and optimized multicore communication

Accelerator Coherence Port small
Accelerator Coherence Port
(View larger block diagram)

Utilized during the development of the multicore benchmarking framework developed by the industry-led Embedded Microprocessor Benchmark Consortium (EEMBC), the Cortex-A9 MPCore multicore processor demonstrated near linear scalability in a variety of benchmarks, with additional processor units providing up to four times the performance of a comparable single core processor.

Complete Ssystem Solution
Both ARM Cortex-A9 processors include ARM’s application specific architecture extensions, including DSP and SIMD extensions, Jazelle® technology, TrustZone technology and Intelligent Energy Manager (IEM™) technology. In addition, ARM has developed a full range of supporting technology around the new processor to reduce design time and accelerate time-to-market. This complete system solution comprises fabric IP, system design, development and debug tools, and ARM Advantage standard cell libraries and memories.

  • Floating-Point Unit (FPU): The Cortex-A9 FPU provides high-performance single and double precision floating-point instructions.
  • Media Processing: The Cortex-A9 NEON Media Processing Engine (MPE) offers the performance and functionality of the Cortex-A9 FPU plus the ARM NEON Advanced SIMD instruction set first introduced with the Cortex-A8 processor for accelerated media and signal processing functions.
  • Physical IP: Providing a wide range of products including standard cell libraries and memories required for low-power and high-performance implementations on a Cortex-A9 processor. The standard cells include power management kits that enable dynamic and leakage power saving techniques such as clock gating, multi-voltage islands and power gating. The memory compilers are also offered with advanced power-saving features. The Physical IP products, which are immediately available for download at, can be used for both single and multicore implementations.
  • Fabric IP: The Cortex-A9 processor is supported by a comprehensive set of PrimeCell® fabric IP components including the PL341 DDR2 dynamic memory controller, the PL351 static memory controller, plus the PL301 AXI configurable interconnect. In addition, the PL310 L2 Cache Controller has been developed to provide an optimized L2 cache controller that can match the performance and throughput capability of the Cortex-A9 processors in high frequency designs. The AMBA® Designer tool enables SoC developers to configure and stitch complex AXI interconnect sub-systems and export RTL to standard EDA flows.
  • System Design: The ARM RealView® SoC Designer tool provides rapid architectural exploration and performance analysis of Cortex-A9 processor-based systems and enables early development of software drivers and timing critical code long before hardware is available. The RealView System Generator tool offers ultra-fast modelling capability for deployment of Cortex-A9 processor-based virtual platforms running native ARM code to large communities of software developers. Cycle based and programmers’ view models of the Cortex-A9 processor, for use in RealView tools, will be available in 2Q 2008.
  • Debug: The Cortex-A9 processor uses ARM CoreSight™ technology to speed complex debug and reduce time-to-market. The processor includes Program Trace Macrocell technology to enable program-flow trace capabilities for full visibility into the processor’s instruction flow, and implements the ARMv7 architecture-compliant debug interface to enable tools standardization and higher debug performance. The available CoreSight design kit for the Cortex-A9 processor extends the debug and trace capability to cover the entire system-on-chip including multiple ARM processors, DSPs, and intelligent peripherals.
  • Software Development: The ARM RealView Development Suite includes advanced code generation tools which will implement Cortex-A9 processor-specific enhancements to deliver exceptional performance and unmatched code density. The tools also support vectorizing compilation for the NEON media and signal processing extensions, enabling developers to achieve product and project cost reductions through the elimination of separate DSPs. Cortex-A9 MPCore multicore processor debug including advanced cross triggering will be supported by the RealView ICE and Trace products. The Cortex-A9 processor will also be supported by a range of hardware development boards supporting system prototyping in FPGA and software development.

Related Links:

Cortex-A9 White Paper (590KB PDF)